Architecture

Lifecycle management for maximum efficiency and minimal latency

In a graph-based architecture, each node must encapsulate a DSP kernel with explicit internal state and well-defined contracts for the preparation (prepare), processing (process), and commit (commit) phases ensuring consistency across stages.

During the prepare phase, formats (channels, stride, and alignment) must be validated, and memory must be requested from pre-sized pools to avoid dynamic allocation on the audio thread. In process, optimized transformations must be applied with 16 or 32-byte alignment, conservative prefetching, and loop unrolling only when it provides measurable gains.

The commit phase must publish read/write counters and update finite state machines (for example, envelope queues, dynamics look-ahead, or fractional resamplers), applying minimal memory barriers to avoid tearing or inconsistencies.

This three-phase design enables pipelining between nodes, reduces intermediate latencies, and improves data locality in L1/L2 caches, especially in long chains with fan-out.

Precision

The numerical pipeline must prioritize stability and precision. Operators that involve accumulation —such as IIR filters, bus summing, or RMS detectors— should perform arithmetic in Float64, while the signal-path should remain in Float32 to reduce memory pressure.

Conversions between dB and linear values, panning laws, and scalings must apply epsilon floors to avoid denormals and preserve smooth gradients in the sub-threshold range. Ramp generators must offer flexible and sample-accurate automation.

Rate selection must be validated during the prepare phase and remain fixed throughout the block, avoiding policy changes during the audio-graph processing.

Processing

High-cost operations —such as convolution or analysis— must be implemented using partitioned FFT with window sizes matched to the context’s blockSize.

In long-tail convolutions (IR/HRTF), small partitions should be used for early reflections (low latency) and large partitions for the tail (high efficiency), with sample-accurate crossfades when switching impulses to prevent artifacts and maintain temporal continuity.

Each kernel must operate over temporary buffers in contiguous memory, allowing the graph to scale to hundreds of nodes without increasing latency.

Block-based processing must guarantee stable and deterministic execution.

CPU and memory resources must be distributed evenly throughout the render cycle, maintaining deterministic behavior even under sustained load.